This invention relates to a method of designing an LSI layout, and more particularly to a method of designing an LSI layout, which makes it possible to achieve an LSI layout which is optimum from the perspective of LSI chip yield per wafer (the number of LSI chips which can be arranged on a single wafer) and manufacturing cost per LSI chip.
Generally, in the initial stage of setting up an LSI layout on a wafer, a so-called floor plan is made at first. The object of this floor plan is to elaborate how to reduce the area occupied by respective LSI chips and also how to improve the performance thereof, thereby roughly setting up the arrangement of LSI chips on the wafer in advance of actually arranging LSI chips and wires distributed thereto on the wafer.
The conventional basic way of thinking about the floor plan has stood on the premise that a reduction of an individual LSI chip size should naturally result in an increase in the number of LSI chips which can be arranged on a single wafer. However, in actual LSI chip production, the number of LSI chips which can be arranged on a single wafer depends not only on the size of the LSI chips, but also on other factors and conditions, for instance the location of various alignment marks which are formed on the wafer and referred to when executing over-printing of various mask patterns by using a light exposure device or an aligner, the placement of one or more Test Element Groups (TEGs) to be mounted on each of the LSI chips for evaluation of respective circuits and processes, and so forth. Therefore, a reduction of the chip size will not necessarily always result in an increase in the number of chips which can be arranged on each wafer, i.e. the LSI chip yield per wafer. Accordingly, even though a reduction of the LSI chip size could be accomplished by expending a huge number of man-hours on the LSI layout design, it might happen that the LSI chip yield will be left unchanged after all, or that the LSI chip yield is decreased contrary to expectations, because of restrictions on the aligner that can be used, restrictions on the location of various alignment marks and the TEG(s), and other restrictions. This has raised a problem to be solved.
Also, with the prior art method, there has sometimes occurred such a case during design work on the mask for a new LSI, after once completing the LSI layout, that various marks and TEG(s) cannot be located on the mask. In the worst such case, the LSI layout cannot but be revised, which results in a large extension of the time period required for development of the new LSI.
As mentioned above, in the prior art method of designing an LSI layout, the design is carried out focusing only on the LSI chip itself, and the arrangement of LSI chips in association with the mask is omitted from consideration, so that a reduction of the LSI chip size fails to result in a reduction of the manufacturing cost, or during the design work for masks after completion of the LSI layout, an LSI chip arrangement satisfying a target LSI chip yield per wafer cannot be realized. Such results have been raised as problems to be obviated.
Accordingly, the present invention has been made in view of the above-mentioned problems involved in the prior art method of designing an LSI layout, and an object of the invention is to provide a novel and improved method of designing an LSI layout which makes it possible to determine, at the stage of designing the LSI layout, how much the LSI chip size is to be reduced in order to realize an optimum LSI layout with respect to the LSI chip yield per wafer and the manufacturing cost per LSI chip.
Another object of the invention is to provide a novel and improved method of designing an LSI layout which makes it possible to determine at the stage of designing the LSI layout, whether or not LSI chips can be arranged on the wafer, thereby eliminating the step of modifying the LSI layout which might be required depending on the results obtained at the mask design stage.
In order to solve the problems mentioned above, the present invention provides a method of designing an LSI layout which is used at the stage of making an LSI layout plan for each of a plurality of LSI chips before entering into the design of the masks, and which includes a step of judging whether or not all the LSI chips can be arranged on a single wafer along with other (nonelectronic) components (i.e., those which are to be arranged with LSI chips on the same wafer such as TEGs and alignment marks), based on a given LSI chip size and referring to information regarding these other components.
According to the constitution of the above method, it becomes possible, in the LSI layout work before designing the mask, to judge whether or not the LSI layout can be actually realized, based on the currently given LSI chip size. Therefore, this eliminates the step of modifying the LSI layout which might be caused depending on the mask design.
Furthermore, in judging the possibility of arranging the LSI chips and other components on the wafer, it is preferable to take account of the information on these components other than the LSI chip, such as the information on various marks, the information on the TEG(s), and so forth.
In order to solve the problems mentioned above, the present invention still provides a method of designing an LSI layout which is used during the stage of making an LSI layout plan for each of a plurality of LSI chips before entering the stage of designing the masks, wherein there are included steps of calculating an LSI chip yield per wafer based on the given LSI chip size, and/or a step of calculating a manufacturing cost per LSI chip based on the given LSI chip size.
According to the constitution of the above-mentioned method, it becomes possible, during the LSI layout work, to take account of the LSI chip yield per wafer and/or the manufacturing cost per LSI chip, so that it can be judged what LSI chip size is optimum for low cost manufacturing of the LSI chips. Therefore, this contributes to an enhancement of the efficiency in the development of the LSI.
A given LSI chip size used as the basis for a judgment in the method according to the invention, may be a temporary (provisional) LSI chip size which is calculated based on the basic design data, or may be a later stage LSI chip size, employed at a stage after the arranging and wiring of all the LSI chips and other (nonelectronic) components on the wafer have been completed.
Furthermore, as the method of the invention can be applied in such a manner that a plurality of LSI chip sizes may be given, it becomes possible to judge the possibility of arranging all the LSI chips and other components on one wafer for each LSI chip size. If the method is applied such that the LSI chip yield per wafer or the manufacturing cost per LSI chip is calculated with regard to each LSI chip size, the designer may determine which LSI chip size is optimum for the LSI layout.
The aforementioned objects, features and advantages of the invention will become more clear from the following detailed description of the invention, taken in conjunction with the accompanying drawings.